1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit device and particularly to a protection circuit for protecting an internal circuit against an external surge voltage The invention more particularly relates to a layout of an input protection circuit for reducing the chip area and enhancing the resistance to the surge
2. Description of the Background Art
In a semiconductor integrated circuit device (MOS integrated circuit device) having an MOS transistor (insulated gate type field effect transistor) as a component thereof, a gate insulating film of an input transistor receiving an external signal is made relatively thin for implementing its high speed operation (for decreasing an absolute value of the threshold voltage). In the MOS transistor having such a thin gate insulating film, the gate insulating film is broken by discharge of the static electricity For example, since the breakdown voltage of a silicon oxide film is approximately 7.multidot.10.sup.6 V/cm, a gate oxide film (silicon oxide film) having its film thickness of 10 nm suffers the dielectric breakdown when a voltage of 7V is applied thereto. The source of such a high input voltage is the human body, package insertion device, test device, running system operation, lightning, and the like. If the source is the static electricity generated from the human body, for example, the peak value of the current may reach several amperes The input protection circuit is provided in order to prevent transmission of a transient high voltage (surge voltage) due to such static electricity to an internal circuit.
FIG. 14 shows one example of a structure of a conventional input protection circuit. Referring to FIG. 14, an input protection circuit IPC includes: a resistance element R1 connected between a pad PD and a node NA; a resistance element R2 connected between node NA and a node NB; a field transistor FT connected between node NA and a ground node GND and having its gate connected to ground node GND and having a field insulating film as the gate insulation film; and an n channel MOS transistor IF connected between node NB and a ground node GND and having its gate connected to ground node GND. The gate insulating film of MOS transistor IF is similar to that of an ordinary MOS transistor. Pad PD is connected to a frame lead FL constituting an external terminal via a bonding wire BW.
An internal circuit INC which operates responsive to a signal potential applied onto node NB includes at the first input stage, for example, a CMOS inverter constituted by a p channel MOS transistor PQ and an n channel MOS transistor NQ. The source of p channel MOS transistor PQ is connected to a power supply node VCC, and the source of n channel MOS transistor NQ is connected to a ground node GND.
Resistance element R1 limits a surge current flowing into input protection circuit IPC. Field transistor FT is turned on when a voltage level on node NA attains to at least a prescribed voltage because of the avalanche breakdown or the punch-through so that it discharges the surge voltage transmitted to node NA to ground node GND at a high speed.
Resistance element R2 has its resistance value made larger than that of resistance element R1 Resistance element R2 has a function of preventing transmission of the surge voltage on node NA to node NB during discharging of the surge voltage by field transistor FT.
MOS transistor IF has two functions. One is to absorb a small abnormal negative surge voltage transmitted to node NB by turning on to transmit a ground voltage GND on ground node GND (the node and the voltage on the node are represented by the same reference characters) to node NB. The other function is to determine whether pad PD and frame lead FL are connected normally. Specifically, when a negative bias voltage is applied to frame lead FL to set node NB at the negative voltage level, MOS transistor IF is rendered conductive so that a current flows from ground node GND to frame lead FL via internal node NB and pad PD. By externally detecting the current, whether bonding wire BW is correctly connected or not can be determined. MOS transistor IF does not have a large surge voltage applied thereto and has a function of clamping a negative voltage level on node NB at a -Vth level, where Vth represents a threshold voltage of MOS transistor IF.
FIG. 15 schematically shows a cross sectional structure of field transistor FT shown in FIG. 14. Referring to FIG. 15, field transistor FT includes high-concentration N type impurity regions 102 and 104 formed with a space therebetween at a surface of a P type semiconductor substrate region 100, and a field insulating film (LOCOS film) 106 formed between these impurity regions 102 and 104. N type impurity regions 102 and 104 are separated from other elements by field insulating films (LOCOS films) 108a and 108b formed along their outer peripheries.
In the structure of field transistor FT shown in FIG. 15, impurity region 102 is connected to node NA, and impurity region 104 is connected to ground node GND. A gate electrode layer 107 is formed over field insulating film 106 and is electrically connected to N type impurity region 104.
When a transient high voltage surge is applied to node NA, the potential at N type impurity region 102 increases so that N type impurity region 102 and P type semiconductor substrate region 100 reach a highly reverse-biased state. Because of the high voltage applied to the N type impurity region, a depletion layer expands and a lateral parasitic bipolar transistor of an npn structure having impurity region 102, substrate region 100 and impurity region 104 respectively as collector, base and emitter is turned on through the punch-through phenomenon. Accordingly, the high voltage applied to node NA is transmitted to ground node GND via impurity region 102, substrate region 100 and impurity region 104 to be absorbed by the ground voltage supply source.
When the parasitic bipolar transistor is turned on, the breakdown phenomenon (avalanche breakdown) occurs at a junction formed between impurity region 102 and substrate region 100, so that a current flows from impurity region 102 to substrate region 100 and the high voltage surge applied to node NA is absorbed via substrate region 100 (Substrate region 100 is biased at a prescribed potential level such as a normal ground potential or a negative potential.)
The input protection circuit provided for the signal input pad prevents a destruction of the gate oxide films of MOS transistors PQ and NQ in the internal circuit INC, since even if a high voltage surge is applied to pad PD, the high voltage surge is not transmitted to internal circuit INC.
FIG. 16 is a schematic plan view showing a layout of the field transistor in FIGS. 14 and 15. With reference to FIG. 16, the field transistor has N type impurity region 102 formed in a rectangular shape. Field insulating film 106 is formed to surround N type impurity region 102, and N type impurity region 104 is further formed to surround field insulating film 106. In the structure of the field transistor shown in FIG. 16, the width of field insulating film 106 corresponds to the channel length of the field transistor, and the average length of the inner perimeter and the outer perimeter of field insulating film 106 corresponds to the channel width of the field transistor.
A sufficiently large ratio of the channel width W to the channel length L of the field transistor can be obtained by utilizing the layout shown in FIG. 16. As a result, the current driving capability of field transistor FT can be improved to absorb the surge voltage at a high speed.
Various methods are employed for the input protection circuit in order to absorb the high voltage surge at a high speed and to operate the input protection circuit in a stable state.
FIG. 17 is a schematic plan view illustrating a layout of the input protection circuit. Referring to FIG. 17, resistance element R1 constituted by a diffusion resistance or a polysilicon resistance is connected to conductor lines 112 and 114 which are formed at a first level aluminum interconnection layer placed at its upper layer, respectively via contact holes 122 and 124. Conductor lines 112 and 114 are separated at a portion above a region where resistance element R1 is formed. Conductor line 112 is connected to a conductor line 110 formed at a second level aluminum interconnection layer via a through hole 120. Conductor line 110 is connected to pad PD.
Conductor line 114 in a lateral U-shape form is arranged extending across impurity regions 102 and 104 of the field transistor. Conductor line 114 is electrically connected to impurity region 102 via contact holes 128a and 128b. Impurity region 104 is electrically connected via contact hole 126 to a conductor line 116 formed at the first level aluminum layer and placed in parallel with conductor line 114. A conductor line 118 opposite to conductor line 116 with conductor line 114 therebetween is formed at the first level aluminum interconnection layer. Conductor line 118 is electrically connected to impurity region 104 via contact hole 130, and also connected to a ground line (not shown) formed at the second level layer aluminum interconnection layer located at its upper layer via through hole 132. Conductor lines 114 and 118 extend over the field insulating film and act as gate electrodes of the field transistor.
After passing through the field transistor, conductor line 114 has an end portion electrically connected to one end of resistance element R2 formed of a polysilicon or a diffusion layer via contact hole 134. The other end of resistance element R2 is connected to a conductor line 138 formed at the first level layer aluminum interconnection layer via contact hole 136. Conductor line 138 is electrically connected to the gate and drain of MOS transistor IF and the gate of the MOS transistor in the internal circuit (not shown).
FIG. 18 schematically shows a cross sectional structure taken along the line 17A-17A' shown in FIG. 17. Referring to FIG. 18, the field transistor includes impurity regions 102 and 104 formed at semiconductor substrate region 100 having a space therebetween, and field insulating film 106 formed between impurity regions 102 and 104. Impurity region 104 is connected to conductor line 118 via contact hole 130. Conductor line 118 extends over field insulating film 106, and connected to a conductor line formed at the second level aluminum layer (not shown in FIG. 17) via contact hole 132.
Impurity region 102 is electrically connected to conductor line 114 via contact holes 128a and 128b separated from each other. Impurity region 104 is connected to conductor line 116 formed at the first layer aluminum interconnection layer via contact hole 126.
In the structure shown in FIGS. 17 and 18, contact holes 122, 124, 126, 128a, 128b, 130, 134, and 136 have round shaped edges. By forming the edges of the contact holes into rounded shapes, prevention of concentration of an electric field at the edge portion of the contact hole, as well as prevention of occurrence of a high electric field and concentration of a current at the edge portion of the contact hole are possible.
Further, it is possible to prevent a current generated by the high electric field from locally concentrating and being accelerated to break the PN junction. Similarly, through holes 120 and 132 have rounded edges so that it is possible to prevent acceleration of electrons due to the concentration of the high electric field at the edge portion which causes an open-circuit of an interconnection line due to aluminum migration or the like. Further, these contact holes and through holes have sufficiently large areas to allow a current to spread and flow over a wide area. As a result, an interconnection line is not fused off by the heat generated due to the concentration of the power. Further, conductor lines 110, 112 and 114 respectively have sufficiently wide width, and resistance element R1 also has sufficiently large width, so that occurrence of the fusion thereof caused by the heat generation due to the concentration of the current is prevented.
The areas of impurity regions 102 and 104, and the areas of corresponding contact holes 126, 128a and 128b, and 130 are also made sufficiently large, so that the concentration of the power at impurity regions 102 and 104, and those contact hole portions can be prevented. Since impurity region 102 and conductor line 114 are electrically connected via two contact holes 128a and 128b, the areas of the contact holes are equivalently increased to prevent the occurrence of the concentration of the current.
Edge portions of impurity regions 104 and 102 facing field insulating film 106 are formed into rounded shapes. Accordingly, occurrence of the high electric field at the portion adjacent to the field insulating film to cause degradation of the field insulating film is prevented.
In order to prevent the destruction of the input protection circuit itself due to the high voltage surge as described above, some methods such as (i) to prevent local concentration of power consumption, and (ii) to prevent occurrence of the concentration of the electric field are employed. In order to realize high speed response of the input protection circuit to the high voltage surge, the value of the ratio between the channel length and the channel width of the field transistor, the resistance value of resistance element R2, and the like are optimally determined.
FIG. 19 schematically shows a layout of power supply interconnection lines and signal interconnection lines in the input protection circuit portion. With reference to FIG. 19, an interconnection layout for a pad PD arranged in a central region of a semiconductor chip (LOC (lead-on-chip) structure) is shown as one example.
In FIG. 19, at one side of pad PD, wide metal interconnection lines 140a and 140b are placed and narrow metal interconnection lines 142a and 142b are placed between metal interconnection lines 140a and 140b. Metal interconnection 140b is formed at a layer overlying resistance element R2.
At the other side of pad PD, narrow metal interconnection lines 142c-142f for transmitting a signal are placed, and a wide metal interconnection line 140c are further placed. Wide metal interconnection lines 140a, 140b, and 140c are, for example, a power supply line for transmitting the supply voltage or a ground line for transmitting the ground voltage.
When a high voltage surge is applied to pad PD, a large current of a few amperes, for example, flows through resistance element R1 and field transistor FT. As a result, the Joule's heat is generated at the resistance of resistance element R1 and at the contact portion of the field transistor FT (connection portion of the impurity region and the aluminum conductive layer and the PN junction between the impurity region and the substrate region). The large current could cause fusion of the upper layer metal interconnection line because of the generation of the heat. Therefore, the metal interconnection line is not arranged at a layer overlying resistance element R1 and field transistor FT in the input protection circuit. Under metal interconnection line 140b, resistance element R2 is placed. In this case, the large current has been absorbed by resistance element R1 and field transistor FT already, so that the large current does not flow through resistance element R2 and the amount of the generated heat is small. By placing metal interconnection 140b at the layer overlying resistance element R2, an effective area occupied by resistance element R2 on the chip can be reduced
Since an interconnection cannot be made over field transistor FT and resistance element R1, conductor line 114 connecting resistance element R1 and field transistor FT is formed to have an L-shape, and pad PD, resistance element R1 and field transistor FT are arranged in a line in order to reduce the chip area occupied by field transistor FT and resistance element R1 in the input protection circuit. Accordingly, the effective area occupied by the input protection circuit on the chip is reduced. (The area of the interconnection is kept as large as possible.)
In the input protection circuit, the minimum value of the energy of the high voltage surge to be absorbed is absolutely determined (e.g. the high voltage surge is 2000V in the case of the discharging from the human body), making the reduction of the layout area difficult. Especially, in order to avoid concentration of the power consumption in the input protection circuit when the high voltage surge is applied, the minimum values of the line width of resistance element R1, and the areas of the impurity region and the contact portion of the field transistor are determined independently of the chip size of the semiconductor device. Further, since various methods for avoiding concentration of the electric field and the power are employed in the layout of the input protection circuit as describe above, modification of the layout of the input protection circuit is not easy to make.
The ratio of the area of the input protection circuit to the semiconductor chip area is increasing. The area of the input protection circuit occupying the chip area is further increasing with the miniaturization of the interconnection pattern.
In order to make the occupation area of the input protection circuit as small as possible, pad PD, resistance element R1, and field transistor FT are aligned to make the area where the interconnection line can be placed as large as possible as shown in FIG. 19. The pad is arranged aligning along the direction of the alignment thereof since normally the interconnection is not arranged in this region. (A bonding wire is connected to pad PD.)
An efficient layout for reducing the interconnection area cannot be obtained since the metal interconnection line cannot be arranged at a layer overlying the input protection circuit. As a result, it becomes impossible to reduce the area occupied by the interconnection.
FIG. 20 shows an arrangement of the input protection circuits for a plurality of pads. Referring to FIG. 20, pads PDa-PDn are alignedly arranged. Input protection circuits IPCa-IPCn are provided respectively for pads PDa-PDn. Input circuits INCa-INCn are provided respectively corresponding to input protection circuits IPCa-IPCn. Transistors of input circuits INCa-INCn as their components are miniaturized for higher integration. On the other hand, the components of input protection circuits IPCa-IPCn cannot be scaled down according to the miniaturization of input circuit INCa-INCn, and their absolute sizes are predetermined. As the number of pads PDa-PDn increases, the ratio of the area of input protection circuits IPCa-IPCn which occupies the semiconductor chip increases to impede the reduction of the chip size. When the number of such input pads PDa-PDn increases, the number of input protection circuits IPCa-IPCn accordingly increases. As a result, the region where the interconnection cannot be arranged increases to prevent reduction of the interconnection layout area, and efficient reduction of the layout area of the interconnection becomes impossible.